An integrated circuit chip is fabricated according to a design layout. A typical design layout has polygonal shapes arranged in different layers, where each layer is associated with a certain step in manufacturing process. A modern integrated circuit chip has many layers comprising active devices, interconnecting conductors, and via layers. The active devices are responsible for amplification or switching while interconnect and vias are responsible for wiring the active devices together.
On an integrated circuit chip, interconnection resides in different wiring or routing layers sandwiched by layers of inter layer dielectric. Vertical electrical connections between interconnect layers are accomplished by forming via holes in the inter layer dielectric and then fill them with a conducting material. A special kind of vertical connection is the Ohmic contact, or contact in short, to the semiconductor active device. For the purpose of this disclosure, the terms contact and via are interchangeable. Both contacts and vias are represented by rectangular geometries drawn in a special contact or via layer that specify the size and position of the hole to be made on inter layer dielectric. A design layout typically has one contact layer and many via layers.
In chip manufacturing, the design layout of a via layer is first mapped to a corresponding photomasks plate. Vias holes on the wafer are formed by projecting the image of the photomask onto the wafer that is coated with photoresist. The portion of photoresist inside the via area is exposed by ultra-violet (UV) light. The exposed photoresist is dissolved in a subsequent development step, revealing the insulating material to be removed. An etch step that follows removes the insulating material inside via area and forms the actual via hole. To form the conductive path, the via hole is filled with conductive material that connects the top and bottom conductive layers. For the purpose of this disclosure, we call both contact holes and via holes as via holes.
In order to minimize the chip area, the size of via hole is made as small as possible. As the degree of integration increases, the number of vias on a chip has reached many billions. At these large numbers, even a very low failure rate can result in significant number of actual chip failures. As a result, via failure become one of the main causes for chip malfunction.
In order to improve the manufacturing yield, method such as via doubling has been employed in prior art layout [1]. In this scheme, more than one vias is inserted to replace a single via whenever space is available. This operation is performed without generating design rule violations or increases in chip area.
Conventional via doubling inserts additional vias of the same size into the available space. This means the available space must be large enough to accommodate at least two vias plus the minimal via-to-via spacing constraints. Locations where the area is not sufficient for two vias could not benefit from this approach. In addition, the area required for placing an additional via contributes to an increase the capacitance that slows down the circuit operation. Further, it is more difficult to manufacture a pair of small, closely spaced vias using photolithography than one via with an increased area.
The concept of improving yield using an enlarged via to replace a via of minimal size was proposed by Allen et. al. [2], where the size of a via is increased whenever there is space for it to expand without violating design rules. In theory, an expanded via would have better immunity to defects and easier to open in a lithography process.
In practice, however, using variable via and contact sizes lead to serious control problem in manufacturing. The actual contact or via sizes on the chip follows a nonlinear relationship with its drawn size. A larger contact in the drawing becomes even larger on the wafer if the minimal sized contact is to stay on target. Similarly, an increase in the dimension in one direction also causes the image to bloat in the perpendicular direction.
The reason for the non-linear relationship comes from the via size selection. In order to save chip area, via size is selected to be below the linear imaging regime where geometric optics ensures linear scaling. The size of a via hole in a layout drawing is typically smaller than the UV wavelength used for exposing the via. Although the physical size of the hole on the photomask is typically 4 to 5 times larger than the drawn value in the layout, the diffraction effect is very strong during the imaging of the contact and via holes. Under this condition, one can still control the recipe as long as only one type of hole is required.
The difference in size between the drawn and the actual wafer hole becomes even larger when we further consider the etching step in forming the hole on the inter layer dielectric. The etch rate for a bigger hole is faster as the transport of reactive species becomes less constricted as the hole gets bigger.
When vias of different drawn size distort in different ways due to complicated processing physics, it becomes very difficult to control the amount of overlap, or via coverage, on the bottom and top connections for the via. Vias could become only partially covered by the top and bottom conductor, which could potentially lower the chip yield.
The second difficulty is the lack of automatic means to determine the appropriate contact or via size during layout design. Due to the large number of contact and vias, the process of deciding their size on an individual basis becomes impractical. As a result, variable via size are not used for signal connections in circuits such as random logic.
In a highly repetitive product such as the cell bank of a dynamic random access memory, flash memory, and static random access memory, a few handcrafted cells are arrayed to cover a large portion of the chip. For these special, highly repetitive products, variable contact shape have been used to reduce electrical resistance in tight spaces [2].
This disclosure proposes methods for the implementing variable via sizes in an integrated device containing a large number of irregularly spaced circuit elements such as random logic circuits, data path circuits, an element of field programmable gate array (FPGA), radio-frequency circuits, and most of the analog circuitry.